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library IEEE;
use ieee.std_logic_1164.all;

entity direct_sync is
    generic (
        C_AWIDTH    : integer := 24;
        C_DWIDTH    : integer := 16;
        C_BASEADDR  : std_logic_vector := x"B2000000";
        C_HIGHADDR  : std_logic_vector := x"B27FFFFF"
    );
    port (
        SYSCLK      : in    std_logic;                      -- Clock
        RESET       : in    std_logic;                      -- Reset
        SA          : in    std_logic_vector(C_AWIDTH-1 downto 0);  -- Address
        CS3_N       : in    std_logic;                      -- Chip Select3
        EB1_N       : in    std_logic;                      -- Enable Byte(15:8)
        RW_N        : in    std_logic;                      -- Read Write 
        RDY_N       : out   std_logic;                      -- Ready
        SD          : inout std_logic_vector(C_DWIDTH-1 downto 0)   -- Data
    );
end direct_sync;

architecture Behavioral of direct_sync is

signal reg0     : std_logic_vector(C_DWIDTH-1 downto 0);    -- Register
signal data_o   : std_logic_vector(C_DWIDTH-1 downto 0);    -- Output Data
signal RDY_d1   : std_logic;                                -- RDY Delay
signal RDY_N_w  : std_logic;                                -- RDY wire
signal EB0_N    : std_logic;                                -- Enable Byte(7:0)

begin

    EB0_N <= SA(0);

-------------------
-- RDY Signal Gen
-------------------
    process(SYSCLK, RESET)
    begin
        if RESET = '1' then
            RDY_d1 <= '1';
            RDY_N_w <= '1';
        elsif SYSCLK'event and SYSCLK = '1' then
            RDY_d1 <= CS3_N;
            RDY_N_w <= RDY_d1;
        end if;
    end process;

    RDY_N <= RDY_N_w;

------------------
-- Write Access
------------------
    process(SYSCLK, RESET)
    begin
        if RESET = '1' then
            reg0 <= (others => '0');
        elsif SYSCLK'event and SYSCLK = '1' then
            if CS3_N = '0' and RW_N = '0' and RDY_N_w = '0' then
                case SA(3 downto 1) is
                    when "000" =>
                        if EB1_N = '0' then
                            if EB0_N = '0' then
                                reg0 <= SD;
                            else
                                reg0(15 downto 8) <= SD(15 downto 8);
                            end if;
                        else
                            reg0(7 downto 0) <= SD(7 downto 0);
                        end if;
                    when others => null;
                end case;
            end if;
        end if;
    end process;

------------------
-- Read Access
------------------
    process(SYSCLK, RESET)
    begin
        if RESET = '1' then
            data_o <= (others => '0');
        elsif SYSCLK'event and SYSCLK = '1' then
            if CS3_N = '0' and RW_N = '1' and RDY_N_w = '0' then
                case SA(3 downto 1) is
                    when "000" => data_o <= reg0;
                    when others => data_o <= (others => '0');
                end case;
            end if;
        end if;
    end process;

    SD <= data_o when CS3_N = '0' and RW_N = '1' and RDY_N_w = '0' else (others => 'Z');

end Behavioral;